The invention uses various materials which are electrically either conductive, insulating or semiconducting, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor". The invention refers to a method of controlling addressed devices, and is not restricted to implementations which involve memory devices or semiconductor devices.
An electronic circuit is chemically and physically integrated into a substrate such as a silicon wafer by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive, for conductor and resistor fabrication. They can also be of differing conductivity types, which is essential for transistor and diode fabrication. Degrees of resistance, capacitance, or conductivity are controllable, as are the physical dimensions and locations of the patterned regions and layers, making circuit integration possible.
In this disclosure, "n type material" denotes silicon that has been doped with atoms having more than four valence electrons (group V or higher), such as arsenic or phosphorous which introduce negatively charged majority carriers into the silicon, and "p type material" denotes silicon doped with atoms having less than four valence electrons (group III or lower), such as boron, which introduce positively charged majority carriers. The majority charge carrier type is also referred to as conductivity type. A plus or minus superscript on an n or p indicates heavy or light doping, respectively. "Poly" denotes polycrystalline silicon.
In a dynamic random access memory (DRAM), a plurality of cells consisting of capacitors are each connected to respective access devices. The access device is usually a field effect transistor, and is used to conduct current between the capacitor and address circuitry, in order to charge the capacitor to a logic level and to read that charge.
The memory cells of dynamic random access memories are comprised of two main components: a field-effect transistor (FET) and a capacitor. In DRAM cells utilizing a conventional planar capacitor, far more chip surface area is dedicated to the planar capacitor than to the field-effect transistor. The gate of the FET and an interconnect word line are formed from an etched polycrystalline silicon layer. The FET has source and gate connections to bit line and word line connections. The capacitor has a lower plate formed from an n+ silicon substrate. The upper capacitor plate is formed from a layer of polycrystalline silicon, and is electrically insulated from upper plate by a dielectric layer.
Planar capacitors have generally proven adequate for use in DRAM chips up to the one-megabit level, but appear to be unusable beyond the one-megabit DRAM level when constructed with conventional dielectric materials. As component density in memory chips has increased, the shrinkage of cell capacitor size has resulted in a number of problems. Firstly, the alpha-particle component of normal background radiation will generate hole-electron pairs in the n+ silicon substrate plate of a cell capacitor. This phenomena will cause the charge within the affected cell capacitor to rapidly dissipate, resulting in a "soft" error. Secondly, the sense-amp differential signal is reduced. This aggravates noise sensitivity and makes it more difficult to design a sense-amp having appropriate signal selectivity. Thirdly, as cell capacitor size is decreased, the cell refresh time must generally be shortened, thus requiring more frequent interruptions for refresh overhead. The difficult goal of a DRAM designer is therefore to increase or, at least, maintain cell capacitance as cell size shrinks, without resorting to processes that reduce product yield or that markedly increase the number of masking and deposition steps in the production process.
Several methods for providing adequate cell capacitance in the face of shrinking cell size are either in use or under investigation. Basically, the efforts fall into two categories. Efforts within the first category are aimed at creating complex three-dimensional capacitors; those within the second are aimed at improving the dielectric of the planar capacitor.
The three-dimensional technique currently receiving the most attention involves the creation of "trench" capacitors in the cell substrate. The trench is employed to provide greater plate area, and hence, greater capacitance. The lower plate and upper plates are still insulated with a dielectric layer, but these layers are arranged vertically, when viewed in cross section with the substrate horizontal. DRAM chips employing trench capacitors have been built by a number of European, Japanese and U.S. companies, including Texas Instruments Inc., Nippon Electric Company, Toshiba, Matsuchita and Mitsubishi Electric Corporation. There are several problems inherent in the trench design, not the least of which is trench-to-trench capacitive charge leakage which is the result of a parasitic transistor effect between trenches. Another problem is the difficulty of completely cleaning the capacitor trenches during the fabrication process; failure to completely clean a trench will generally result in a defective cell.
Another three-dimensional technique, which is being used by Mitsubishi Electric Company, Hitachi, and Fujitsu Ltd., is the stacking of capacitor plates between dielectric layers on the DRAM cell surface. Both the lower plate and the upper plate are made from n-type polycrystalline silicon layers and are separated by a dielectric layer and arranged in a high-profile cell which requires more stringent process control for the connection of bit line to FET source. The capacitor thus formed also fails to use the n+ silicon substrate extension of FET drain as a plate of capacitor.
Alternatively, other schemes involve the use of ferroelectric materials for DRAM cell capacitor dielectrics. Since ferroelectric materials have a dielectric constant more than 100 times that of silicon oxides, the use of such materials has the potential for allowing the size of the DRAM-cell capacitor to be shrunk to one of the smaller cell elements without resorting to three-dimensional structures. Critics of ferroelectric materials point out that such materials suffer from a "wearout" mechanism. In addition, they warn that there are many chemical incompatibilities with the other materials used in integrated circuit fabrication and that the layering of ferroelectric films within integrated circuit structures has not yet been done successfully.
Since the capacitor is very small on a high density DRAM, the cell must be frequently refreshed. This is done by reading the stored logic level in that cell before the logic level is lost through leakage current, followed by rewriting the same value into the cell.
The capacitors consist of conductors separated by dielectric material. The capacitor, despite its small size, must therefore maintain a significant surface area of these conductors and dielectric material in order to store enough charge to provide enough potential and current to be read. Of course, larger capacitors consume more current when charged. It would therefore be advantageous to provide a dynamic random access memory which does not require the use of capacitors for storage of memory logic levels.
In the operation of a field effect transistor, such as a MOSFET, an electrical charge on an electron gate is used to induce a change in electric charge carriers in a semiconductor material, beneath the gate, between source and drain regions. This change changes the conductive status of the semiconductor material beneath the gate. In that manner, an electric potential applied to the gate can modulate current flow across the semiconductor beneath the gate, between the source and drain.
The application of potential to a portion of a semiconductor creates depletion depth region, which is essentially a "hot zone" of injected depletions surrounding that portion of the semiconductor which is charged to the potential.
It is possible to use such a depletion region of a semiconductor as a storage cell in a memory array. The depletion region is charged through a conductive region, such as a source/drain area of a transistor. When the depletion region is used in this manner, logic levels may then be measured by sensing the conductive region.
A high logic level is stored by the formation of the depletion region by causing the region under the conductive portion to be injected with carriers which are injected by a charge potential at the conductive portion. A low logic level is stored by a reduced formation of the depletion under the conductive portion. These logic levels are sensed and periodically refreshed by conduction through the access device.
In an initial concept, the depletion region was located in a semiconductor substrate below source/drain areas of transistors. The source/drain areas were also implanted into the substrate. A doped substrata was located subjacent the depletion region. When a charge is applied to the substrata, current would pass to the source/drain areas if the depletion region is not already charged. This results in an increased voltage level in the cell if the cell had previously had a reduced charge. The preferred location for the substrata was within the substrate, which means that addressing of portions of an array is difficult. This also means that a large portion of the semiconductor device must be brought to an elevated voltage. The formation of the substrata was accomplished by increasing the depth of an implant (such as phosphorous implant) under or through an active area, so that the dopant density profile ("dopant density") peaks are significantly separate in depth, preferably 0.6 microns or more.
In that configuration the depletion layer is located between an area of a substrate which is rendered conductive by doping and a substrata consisting of a doped level below the surface of a substrate. The storage cell is read by measuring potential through the access device, or by measuring punch through voltage between the substrata and the access device. As the level of injected carriers increases, the punch through also increases. A punch through results in a readable increase in current through the access device, thereby providing an indicia of a change in logic level.
The reading of storage cells by causing a punch through to occur means that the read operation will reverse the charge of the cell. Therefore, all cells which are subjected to the charge across the depletion area must be refreshed, or the inversion of the logic levels be otherwise accounted for.
One modification included differentially doping source/drain regions of the access device. This reduces the depletion region on an address line side of the access device and increase the depletion region on the opposite side of the access device, where the injected carriers corresponding to logic levels were stored.